Early-late synchronizer having reduced timing jitter

ABSTRACT

A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises:—delay line ( 56 ) for storing a plurality of consecutive samples (E−1, E, M, L, L+1) of the incoming spread spectrum signal;—three digitally controlled interpolators ( 24, 26, 28 ) for determining by interpolation between consecutive samples an interpolated early sample (e), an interpolated middle sample (m) and an interpolated late sample (1);—two correlators ( 30, 32 ) for calculating an error signal (ξ) as the difference between the energy of the symbols computed from the interpolated early (e) and late (1) samples;—a circuit for generating a control signal (S OUT?) for controlling the interpolation phase of the digitally controlled interpolator ( 24 ) for the early sample (e), and—a digital non-linear filter ( 68 ), for smoothing the control signal (S OUT?) of the interpolator ( 24 ) for the early sample (e), enabling the update operation of the control signal only when the absolute value (|ξ(n)|) of the error signal at a time instant n is smaller than the absolute value (|ξ(n−1)|) of the same error signal at a time instant n−1.

FIELD OF THE INVENTION

The present invention refers to telecommunication systems and inparticular to a method for fine synchronization of a digitaltelecommunication receiver. The invention also relates to a digitalreceiver for use in a CDMA (Code Division Multiple Access) system.

The CDMA access technique currently finds widespread use in thirdgeneration mobile communication systems (e.g. UMTS, CDMA2000) thanks toits higher spectrum efficiency with respect to other access techniques.

In a CDMA system the data sequence is spread by a pseudo noise code(hereinafter “PN code”) having a broader spectrum width. The efficiencyof these systems is highly dependent on the capability of the receiverto continuously maintain precise phase synchronization between thereceived and the locally generated PN code.

In fact, without a precise phase synchronization between the receivedand the locally generated code, the performance loss of the receiver isin the order of several dB even for a mismatch of half of the chipperiod.

The phase synchronization process is usually accomplished in two steps:code acquisition and code tracking. Code acquisition is the initialsearch process that brings the phase of the locally generated code towithin the chip duration (T_(C)=1/F_(C)) of the incoming code. Codetracking is the process of achieving and maintaining fine alignment ofthe chip boundaries between the incoming and locally generated codes.

In particular, the present invention is concerned with the code trackingpart of the receiving apparatus, which is generally implemented in theform of a Rake receiver.

For a digital receiver a key component is the analog-to-digitalconverter (ADC). In several applications the sampling clock rate cannotin any case be synchronized with the incoming signal. For example, oneof these applications is a CDMA base station receiver where the sum ofseveral signals, non-synchronous among each other, are received anddigitised with a single analog-to-digital converter. In these cases, thefine timing synchronisation (i.e. the code tracking) between thereceived and locally generated PN code of each user must be achievedthrough digital methods, as it is not possible to modify the samplingclock phase.

BACKGROUND ART

The code tracking operations are performed by a Synchronisation Unit.Several types of code tracking loops have been extensively applied inpractical applications and the most popular solution is the so-calledEarly-Late synchronizer.

The Synchronisation Unit receives, as input, the baseband signal y(t)from the receiver front-end, oversampled at the frequency f_(s)=N·F_(C)and with at least two samples per chip (N≧2), and feeds a finger of theRake receiver with one sample per chip (i.e. the optimal sample), asshown in FIG. 1. Each finger of the Rake receiver requires its ownSynchronisation Unit because the values of timing offset of thedifferent multi-path components demodulated by the different fingers ofthe Rake receiver are usually not the same.

The fine timing synchronisation can be achieved by performing some kindof interpolation among the received samples, in order to get the exactvalue or, at least, to approximate the received signal in correspondenceof the optimal sampling instants t_(opt). This technique is well knownand is disclosed for example in F. M. Gardner, “Interpolation in digitalmodems—Part I: Fundamentals”. IEEE Trans. Communications vol. 41, pp.502-508, March 1993 or in L. Erup, F. M. Gardner, “Interpolation indigital modems—Part II: Implementation and Performance”.

The optimal sampling instant t_(opt)(t) varies with time due timevariant nature of the wireless channel and corresponds to the instant inwhich the amplitude of the received signal is maximal and,simultaneously, the Inter-Symbol Interference (ISI) is minimal. Bysampling the received signal in correspondence of the optimal samplingtime, it is possible to maximise the Signal to Noise Ratio (SNR) andtherefore minimise the Bit Error Rate (BER) at the output of thereceiver. The optimal sampling time can be observed in the eye diagramas the point of maximum opening, as shown in FIG. 2.

In the following it is described the principle of a Synchronisation Unitbased on the known art. The description is based on the case of a realsignal y(t), but the extension to a complex signal y(t) isstraightforward.

The block diagram of a Synchronisation Unit 1, described in the priorart is, shown in FIG. 3. The considered scheme operates with a feedbackloop. A time continuous signal y(t) is received at the input of theAnalog to Digital Converter 2. The signal y(t) is a sequence of pulseswith period T_(C) and shaped, for example, by a couple of root raisedcosine (RRC) filters${y(t)} = {\sum\limits_{k = 0}^{\infty}{u_{k} \cdot {h\left( {t - {k \cdot T_{C}}} \right)}}}$where u_(k)={−1,+1} is the sequence of transmitted chips and h(t) is theimpulse response of the equivalent Raised Cosine (RC) filter with thefollowing expression${h(t)} = {\frac{\sin\left( \frac{\pi \cdot t}{T_{C}} \right)}{\frac{\pi \cdot t}{T_{C}}} \cdot \frac{\cos\left( {\alpha \cdot \frac{\pi \cdot t}{T_{C}}} \right)}{1 - \left( {2 \cdot \alpha \cdot \frac{t}{T_{C}}} \right)^{2}}}$The unilateral bandwidth of the signal y(t) is equal to$B = \frac{\left( {1 + \alpha} \right)}{2 \cdot T_{C}}$where α is the roll-off of the RRC shaping filters.

The ADC converter 2 takes samples of y(t) at uniform intervals t_(s),which correspond to an ADC sampling frequency of f_(s)=1/t_(s). Thesampling of the analog baseband signal can be performed with differentsampling rates. However, the Nyquist criterion requires a minimum ADCsampling rate of two times the unilateral signal bandwidth, namelyf_(s)≧2·B.

The signal samples y(n·t_(s))=y(n) at the output of the ADC converter 2are provided to the interpolator 4 that computes the interpolated valuesy_(l)(m·t_(l))=y_(l)(m) at intervals t_(l). The goal of the interpolatoris to increase the time resolution after the ADC conversion, so that thetime spacing t_(l) of the samples at the output of the interpolator issmaller that the time spacing t_(s) of the samples at the output of theADC. In general we have $\frac{t_{g}}{t_{1}} = K$where K is an integer number greater than one.

Being the samples y(n) at the output of the ADC not taken incorrespondence of the optimal time instant, the Synchronisation Unitmust first estimate the optimal sampling instant {circumflex over(t)}_(opt) and then compute or approximate the value of y(t) incorrespondence of that instant. The value y({circumflex over (t)}_(opt))is then provided at the output of the Synchronisation Unit for thesubsequent signal processing.

The principle of timing synchronisation through digital interpolation isshown in FIG. 4 for a case of linear interpolation with K=4.

In the example of FIG. 4 the signal y(t) in correspondence of theoptimal sampling instant t_(opt) is approximated with the interpolatedvalue y_(I)(m+3).

The interpolated value y_(l)(m+3) is calculated as follows: first it iscomputed the middle point y_(l)(m+2) between two consecutive samplesy(n) and y(n+1) at the output of the ADC${y_{I}\left( {m + 2} \right)} = \frac{{y(n)} + {y\left( {n + 1} \right)}}{2}$

Similarly, the other two interpolated values y_(l)(m+1) and y_(l)(m+3)are computed as the average between one ADC sample and the interpolatedvalue y_(l)(m+2) calculated in the previous step${y_{I}\left( {m + 1} \right)} = {\frac{{y(n)} + {y_{I}\left( {m + 2} \right)}}{2} = \frac{{3 \cdot {y(n)}} + {y\left( {n + 1} \right)}}{4}}$${y_{I}\left( {m + 3} \right)} = {\frac{{y\left( {m + 2} \right)} + {y_{I}\left( {n + 1} \right)}}{2} = \frac{{y(n)} + {3 \cdot {y\left( {n + 1} \right)}}}{4}}$Of course, by using a more complex interpolation schemie (e.g.parabolic, cubic) or increasing the resolution of the interpolator (i.e.increasing K) it is possible to make more precise the estimate of thereceived signal in correspondence of the optimal sampling instant.

The synchronization unit of FIG. 3 also includes other elements that areessential for the synchronization process. A data filter 5 processes theinterpolated samples and selects the optimal sample for the subsequentsignal processing. The data filter is indicated within the feedbackloop, but it can also be placed outside of the loop. Post-placement maybe advantageous in terms of complexity when the data filter is morecomplicate than the interpolator and a relatively high sampling rate isemployed for interpolation.

The optimal sampling instant t_(opt) is estimated by a timing errordetector block 6 and filtered by a loop filter 7. The goal of the loopfilter is to reject the effect of noise that may affect the optimalsampling time estimate. Finally, the loop filter output drives acontroller 3, which provides the control signal to the interpolator 4.

Starting from the general structure of a Synchronisation Unit, shown inFIG. 3, it is possible to analyse its application in the particular caseof a digital CDMA receiver.

A known solution for performing the code tracking operations in a CDMAreceiver is the so-called Early-Late synchronizer disclosed for examplein John G. Proakis, ‘Digital Communications”, 3^(rd) edition, McGraw-Hill, New York, 1995.

The joint application of the interpolation and the Early-Late conceptfor the synchronisation of a CDMA receiver can be found in R. DeGaudenzi, M. Luise, “A Digital Chip Tuning Recovery Loop forBand-limited Direct-Sequence Spread-Spectrum Signals”. IEEE Trans. OnCommunications, vol. 41, No. 11, November 1993.

An Early-Late synchronizer exploits the symmetry properties of thesignal autocorrelation at the output of the receiver-matched filter.

In the following we suppose that the signal at the input of theEarly-Late synchronizer is sampled with two samples per chip (N=2). Twosubsequent samples at the input of the Early-Late synchronizer are thenseparated in time by T_(C)/2 (with T_(C)=1/F_(C)=chip period).

In order to introduce a suitable mathematical notation for sequenceswith different rates, we denote with k the discrete time index relatedto the chip period so that e(k)=e(k·T_(C)). We also denote with SF thespreading factor. The period of the information symbols before thespreading process is equal to T_(S)=SF·T_(C) and the discrete time indexrelated to this symbol period is equal to (k div SF), where A div B isthe integer part of the quotient between A and B.

Each received chip can be characterised by an early, a middle and a latesamples defined as follows:

early sample: is the sample that anticipates the optimal sampling timeinstant. The early sample is denoted with e_(I)(k) and e_(Q)(k) for thein-phase and in-quadrature component respectively;

middle sample: is the sample that, in the absence of timing errors,corresponds to the optimal sample or equivalently to the peak of thereceived impulse h(t). The middle sample is denoted with m_(I)(k) andm_(Q)(k) for the in-phase and in-quadrature component respectively;

late sample: is the sample that is delayed with respect to the optimalsampling time instant. The late sample is denoted with l_(I)(k) andl_(Q)(k) for the in-phase and in-quadrature component respectively. Thelate sample of a given chip is also the early sample of the next chip.

The definition of early, middle and late samples is clarified in FIG. 5for the in-phase component and in the case of perfect timingsynchronisation. From FIG. 5 it is possible to notice that the middlesample is the one with the higher energy and minimum ISL Consequently,it has to be provided to the Rake finger for the descrambling anddespreading operations.

Moreover, from FIG. 5 it is possible to observe that, if the impulseresponse of the complete system is symmetrical and the system hasachieved a perfect timing synchronisation, then the energies of theearly and late samples are identical.

The two conditions of perfect timing synchronisation can be expressed asfollows:

Perfect timing synchronisation

ε_(m)=m_(I) ²(k)+m_(Q) ²(k)=maximum

Perfect timing synchronisation

ε_(e)=e_(I) ²(k)+e_(Q) ²(k)=ε_(I)=l_(I) ²(k)+l_(Q) ²(k)

where ε_(e), ε_(m), ε_(l) are the energies of the early, middle and latesamples respectively.

In the presence of noise the identification of the sample with maximumenergy is usually difficult. Instead of sampling the signal incorrespondence of the peak, the Early-Late synchronizer identifies theoptimal sampling instant through the second condition: the energy of theearly and late samples has to be equal or, in other words, thedifference between the two energies must be reduced to zero(ε_(e)−ε_(l)=0). When such condition is fulfilled the sample betweenearly and late (i.e. the middle) is the optimal sample to be provided tothe Rake finger.

Taking into account that in a CDMA system the signal to noise ratio onthe channel is very low, the condition ε_(e)−ε_(l)=0 must be verified onthe symbols after the operations of despreading and integration.Averaging over SF samples leads to mean values of the early and latesample energies and reduces the energy fluctuations due to noise andinterference from other users.

A simplified block diagram of a prior art Early-Late synchronizer isshown in FIG. 6 for the general case of a real PN (Pseudo Noise) codec_(e)(k). However, the same scheme is valid in case of complex PN codeby simply replacing each couple of real multiplication units with onecomplex multiplication unit.

The Early-Late synchronizer of FIG. 6 uses two correlators: the firstperforms the despreading and integrate and dump operations on the earlysamples while the second correlator performs the same operations on thelate samples. The outputs of the two correlators are then squared inorder to get the energy of the despreaded symbols, to remove themodulation of the data sequence and the phase rotation introduced by thepropagation channel. Finally, an error signal ξ is computed by takingthe difference of the two-correlator outputs.

After the operations of despreading, integration, squaring and sum ofthe in-phase and in-quadrature components the error signal, for acertain timing error τ=t−t_(opt), is given byξ(k div SF)=E(k div SF)−L(k div SF)

The characteristic of the Early-Late synchronizer in terms of errorsignal ξ as a function of the timing error τ is shown in FIG. 7. TheEarly-Late characteristic, due to its particular shape, is usuallyreferred to as S-curve.

From FIG. 7 we observe that when a timing offset is present (τ≠0), theerror signal ξ at the output of the Early-Late synchronizer is nonzeroand the time position of the early, middle and late samples must bedelayed or advanced (depending on the sign of the error) to get theoptimal sampling instant.

An alternative solution for finely adjusting the time position of theearly, middle and late samples, without delaying or advancing theirpositions, consists in using three digital interpolators as shown, inthe particular case of a timing offset τ=T_(C)/4, in FIGS. 8 and 9.

Two of these interpolators are used to compute the early B and the lateL samples while the-third interpolator is used to compute the middle Msample (i.e. the optimal sample with the maximum energy). The early andlate samples are provided to the correlators for the computation of theerror signal ξ, while the middle sample is provided to the Rake fingerfor the subsequent signal processing (descrambling, despreading, channelestimation and compensation, decoding, etc.).

If we consider in FIG. 8 the early E, the middle M and the late Lsamples, we observe that, by means of a linear interpolator, it ispossible to generate, with a certain resolution, all the samples betweentwo subsequent values early E and middle M or middle M and late L In thecase of error signal larger than zero the optimal sampling time isdelayed with respect to the middle M sample and therefore the value ofthe optimal sample can be computed with a linear interpolation betweenthe middle M and the late L samples. In a similar way for an errorsignal lower than zero, the optimal sample is computed by means of alinear interpolation between the early E and the middle M samples.

In order to compute the delayed or advanced version of the samples earlyE and late L, determining the error signal, it can be necessary tointerpolate the early E sample between the previous sample E−1 and themiddle M sample and, in similar way, the late L sample between thesubsequent sample L+1 and the middle M sample, as it is possible toobserve in FIG. 9. Therefore a Synchronisation Unit based on theEarly-Late synchronizer requires the knowledge of five subsequentsamples E−1, E, M, L, L+1 of the incoming signal spaced of T_(C)/2 amongeach other.

The three interpolators are used to finely adjust the time position ofthe early, late and middle samples feeding the correlators and the Rakefinger respectively. These interpolators are controlled by a digitalsignal derived from the error signal ξ of the Early-Late synchronizer.If the loop is correctly designed so to obtain a negative feedback, thesystem automatically minimizes the error signal by converging towardsthe error zero condition. The minimum error condition is equivalent tosay that the middle sample is the one with the maximum energy andtherefore the optimal one.

The time position of the three interpolated samples (early, middle andlate) is moved backward or forward by a time factor δ when the errorsignal is respectively positive or negative. The factor δ represents thetime resolution of the interpolators and it is usually equal to T_(C)/8.

The Early-Late synchronizer is a closed loop system that reaches asteady state when the error signal is exactly zero. In practice, becauseof the finite arithmetic precision of the device, the error signalvaries around the zero value by alternating negative and positivevalues.

Consequently the control signals of the interpolates, which are derivedfrom the sign of the error signal ξ, oscillate around the steady statevalues. Such behaviour allows a continuous tracking of the optimaltiming but, at the same time, introduces an undesired jitter on thetime-position of the middle sample.

The timing jitter introduces a performance degradation in the wholesystem. A known solution for compensating such performance degradationis to increase the time resolution of the interpolators. Neverthelesssuch solution is rather expensive, the complexity of a digitalinterpolator is generally proportional to its resolution, because of themathematical operations required to perform interpolation.

The complexity of the single interpolator affects negatively the chiparea, especially in case of a base station receiver where many of theseinterpolators are required to process the signals of the various users.Each Rake finger of a base station needs six interpolators: early,middle and late for both signal components (I and Q). Moreover if weconsider, as a possible example, a UMTS base station with 64 differentRake receivers, each with N_(f)=8 fingers, it is then evident from thesenumbers that employing interpolators having reduced complexity is aremarkable advantage.

The Applicant has tackled the problem of reducing the timing jitter ofthe middle interpolator, without increasing the time resolution of thecorresponding digital interpolator.

The Applicant observes that, alternating between negative and positivevalues of the error signal around the zero value, although allowing acontinuous tracking of the optimal timing, does not give any positivecontribution to the synchronization process. On the contrary, suchbehaviour introduces a timing jitter on the position of the middlesample which influences negatively the whole system performance.

In view of the above, it is an object of the invention to provide anearly-late synchronizer having a reduced timing jitter. Thanks to thereduced timing jitter, it is possible to reduce the resolution of theinterpolators and, consequently, the area of the silicon chip in whichthe system is integrated.

The above and other objects are reached by the method and the devicerealised according to the invention, as claimed in the accompanyingclaims.

SUMMARY OF THE INVENTION

The Applicant has found that, filtering appropriately the control signalof the middle interpolator, which is directly derived from the errorsignal ξ, the timing jitter of the same interpolator can be remarkablyreduced. To this end, the interpolation unit of the device provides fora non-linear filter that smoothes the control signal of the middleinterpolator, enabling the update operation of the control signal onlywhen this effect is generated by an actual reduction of the magnitude(absolute value) of the error signal. In the opposite case, when theabsolute value of the error signal at time n is equal or grater than theabsolute value of the error signal at time n−1, it is assumed that themodification of the control signal is due to an undesired jitter andtherefore it is more convenient to keep the previous value of thecontrol signal.

The method and the device according to the invention allow to reduce, oreven remove, the timing jitter on the middle interpolated sample, thusallowing to simplify the architecture of the interpolators and to reducethe complexity of the whole system, while maintaining optimum systemperformances.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art module of a Rake Receiver;

FIG. 2 is an example of an eye diagram showing an optimal sampling timeinstant;

FIG. 3 is a block diagram of a prior art synchronization unit;

FIG. 4 is a graph showing timing synchronization by means of signalinterpolation;

FIG. 5 is a graph showing early, middle and late samples on a receivedsignal;

FIG. 6 is a simplified block diagram of an Early-Late synchronizer;

FIG. 7 is a graph of en error signal in an Early-Late synchronizer;

FIGS. 8 and 9 show a known principle of digital Early-Late synchronizerexploiting the interpolation;

FIG. 10 is a complete block diagram of a digital Early-Late synchronizerwith feedback loop, according to the invention;

FIG. 11 is a digitally controlled interpolator used in the synchronizerof FIG. 10;

FIG. 12 is a diagram showing the Early-Late spacing as a function oftiming error τ, according to the invention;

FIG. 13 and FIG. 14 are tables illustrating the mathematical operationsrequired to perform a linear interpolation according to the invention;

FIG. 15 is a block diagram of a complete structure of interpolators,according to the invention;

FIG. 16 is a table illustrating the values of control signals of theinterpolators of FIG. 15; and

FIG. 17 is a block diagram of a digital filter used in the structure ofinterpolators of FIG. 15.

A device according to the present invention will now be described indetail with reference to the UMTS (Universal Mobile TelecommunicationsSystem) systems, in the particular case of a UMTS receiver operating inthe FDD mode (Frequency Division Duplex).

A complete Early-Late synchronizer 18, which can be used in a digitalcommunication receiver for maintaining fine alignment between anincoming spread spectrum signal and a locally generated code, is shownin FIG. 10.

The device 18 comprises:

a delay line 56 for storing a plurality of consecutive samples E−1, E,M, L, L+1 of the incoming spread spectrum signal;

a first digitally controlled interpolator 26 for determining byinterpolation between consecutive samples an interpolated early sample(e) anticipating an optimal sampling time instant;

a second digitally controlled interpolator 24 for determining byinterpolation between consecutive samples an interpolated middle sample(m) corresponding to the optimal sampling time instant;

a third digitally controlled interpolator 28 for determining byinterpolation between consecutive samples an interpolated late sample(l) delayed with respect to said optimal sampling time instant;

a first correlator 32 performing the despreading and integrate and dumpoperations on the interpolated early sample (e), and a second correlator30 performing the same operations on the interpolated late sample (l);the outputs of the two correlators are squared in order to get theenergy of the despreaded symbols and to remove the modulation of thedata sequence and the phase rotation introduced by the propagationchannel; finally, an error signal ξ is computed by taking the differenceof the two-correlator outputs;

a low pass filter 22 for averaging the error signal ξ on a certainnumber of symbols;

a circuit 23 for extracting the sign of the error signal ξ;

a control signal generator 66 for accumulating the sign of the errorsignal ξ in an internal register, for the generation of control signalsS_(E), S_(M), S_(L) for controlling the interpolation phases of thefirst 26, second 24 and third 28 digitally controlled interpolators;

a digital non-linear filter 68 for smoothing the control signal S_(M) ofthe second digitally controlled interpolator 24.

The time distance between the interpolated early (e) and late (l)samples varies in relation with the control signals S_(E), S_(M), S_(L),as will be explained in detail below.

The early-late synchronizer 18 is a closed loop control system whosebandwidth is relatively narrow compared to the chip rate F_(C). The lowpass filter 22, used to average the error signal ξ on a certain numbersymbols, determine the loop bandwidth. In order to maintain a precisecode synchronisation, the loop bandwidth must be large enough to trackthe instantaneous delay of the correlation function but sufficientlynarrow to reject the effects of noise and interference.

The system therefore automatically minimizes the error signal byconverging towards the error zero condition. The minimum error conditionis equivalent to say that the middle sample is the one with the maximumenergy and therefore the optimal one.

Each of the digitally controlled interpolators 24, 26, 28 is a device,as the one shown in FIG. 11, receiving three input signals, denoted asy_(E), y_(M), y_(L) and a control signal denoted with SEL. The output ofthe interpolator y_(OUT) is a function of the four inputs,y_(OUT)=ƒ(y_(E),y_(M), y_(L),SEL).

The inputs y_(E), y_(M), and y_(L) are fed with three consecutivesamples of the digital signal y(t) to be interpolated (the samplesstored in the delay line 56). The time position, or interpolation phase,of the interpolated sample can be selected through the control signalSEL, as will be explained later on in detail.

The middle sample is provided to the Rake finger for the furtherbase-band processing and it has to be selected with sufficient precisionin order not to reduce the performance of the receiver in terms of BitError Rate (BER).

The time resolution of the first 26 and third 28 digitally controlledinterpolators is lower than tie time resolution of the second digitallycontrolled interpolator 24. In the embodiment shown in FIG. 10, as theinput samples are time spaced of T_(C)/2, the early and lateinterpolators 26, 28 have a time resolution of T_(C)/4, while the middleinterpolator 24 has a resolution of T_(C)/8.

FIG. 12 illustrates five consecutive received signal samples 56 (E−1, E,M, L, L+1 ), time spaced of T_(C)/2 on a time axis t, and nine differentinterpolation patterns corresponding to nine different timing errors τ(from τ=T_(C)/2 to τ=T_(C)/2). The interpolated early samples are shownin FIG. 12 by square symbols 50, the interpolated middle samples bydiamond symbols 54 and the interpolated late samples by star symbols 52.

As can be seen in FIG. 12, the early-late spacing Δ is variable andtakes the two values T_(C) or 3·T_(C)/4, alternatively, as a function oftiming error τ. The interpolated middle sample 54, computed with aresolution of T_(C)/8, is always taken as the midpoint between the early50 and the late 52 samples in order to ensure the error signalbalancing.

The output values y_(OUT)=ƒ(y_(E),y_(M),y_(L),SEL) of the digitallycontrolled interpolator 24, having a time resolution of T_(C)/8 arelisted in the table of FIG. 13.

The table of FIG. 14 illustrates the output valuesy_(OUT)=ƒ(y_(E),y_(M),y_(L),SEL) of the digitally controlledinterpolators 26, 28, having a time resolution δ=T_(C)/4.

As it is shown in FIG. 14, the mathematical operations required toperform a linear interpolation with resolution δ=T_(C)/4 are only sumsand divisions by two (i.e. right shifts), therefore the hardwarecomplexity of such linear interpolators is much lower than aninterpolator with resolution δ=T_(C)/8.

In FIG. 15 is illustrated the complete structure of theearly-middle-late interpolators for one signal component. The structurehas been shown for the in-phase component I of the signal, however thesame structure is valid also for the in-quadrature Q components.

The block that generates the control signals for the interpolators isshown in FIG. 10 and FIG. 15 as block 66.

The control signal generator 66 receives in input the sign of the errorsignal ξ, computed according to the following rule${{sign}(\xi)} = \left\{ \begin{matrix}{+ 1} & {{{if}\quad\xi} > 0} \\0 & {{{if}\quad\xi} = 0} \\{- 1} & {{{if}\quad\xi} < 0}\end{matrix} \right.$

and provides as output the control signals S_(E), S_(M) and S_(L) forthe three interpolators of the early, middle and late samplesrespectively. The control signals are the same for both the in-phase andin-quadrature component interpolators.

The control signal S_(M), passing through the digital filter 68 forreaching the SEL input of interpolator 24, is obtained by accumulatingthe sign of the error signal, with a saturation for values larger than 4or smaller than −4. The algorithm employed for the generation of thesignal S_(M) is the followingS _(M)(−1)=0S _(M)(n)=S _(M)(n−1)+sign(ξ)if [S _(M)(n)>4] then S _(M)(n)=4if [S _(M)(n)<−4] then S _(M)(n)=−4

The values of the control signals S_(E) and S_(L) for the early and lateinterpolators respectively, can be derived as a function of the controlsignal S_(M) from FIG. 11 and from the table of FIG. 14. In particular,the values of the control signals S_(E), S_(L) and S_(M) as a functionof the timing offset τ are given in the table of FIG. 16.

The expressions of the control signals S_(E) and S_(L) can be computedas a function of the signal S_(M):$S_{E} = {{\left\lfloor \frac{S_{M}}{2} \right\rfloor\quad S_{L}} = \left\lfloor \frac{S_{M} + 1}{2} \right\rfloor}$

where the function └·┘ approximates the argument to the nearest lowerinteger.

According to the invention, the signal S_(M) generated by block 66 isfiltered by the digital filter 68.

The filter 68 is a non-linear filter that smoothes the control signalS_(M) of the middle interpolator 24. The timing jitter is removed byupdating the control signal S_(OUT), and therefore the position of themiddle interpolator, only if the absolute value of the error signal ξ(n)at time n is smaller than the absolute value of error signal ξ(n−1) attime n−I. This assumption is motivated from the fact that it isconvenient to change the position of the interpolator working on themiddle samples (feeding a Rake finger) only when this effect isgenerated by an actual reduction of the magnitude (absolute value) ofthe error signal. In the opposite case, when the absolute value of theerror signal ξ(n) at time n is equal or greater than the absolute valueof the error signal ξ(n−1) at time n−1, we assume that the modificationof the control signal S_(OUT)(n) is due to an undesired jitter andtherefore it is more convenient to keep the previous value of thecontrol signal S_(OUT)(n−1).

The structure of digital filter 68 is shown in detail in FIG. 17. Theabsolute value (calculated by block 70) of the error signal <ξ(n))> attime n, generated in correspondence of the values of the control signalsS_(E)(n), S_(M)(n), S_(L)(n) and filtered by the low pass filter 22, iscompared, by the comparator block 74, with the absolute value of theprevious error <ξ(n−1)>, stored in a register 72. If the module of<ξ(n)> is smaller than the module of <ξ(n−1)>, the position of themiddle interpolator is updated by setting the output S_(OUT)(n) of thedigital filter 68 to the value of S_(M)(n), otherwise the previous valueof the output S_(OUT)(n−1) is hold.

In FIG. 17 it is denoted with “n” the temporal index related to theDPCCH bit period T_(B) so that ξ(n)=ξ(n·T_(B)), where T_(B) is given by:T _(B) =T _(C) ·SF _(DPCCH)

The comparator block 74 generates an output C_(OUT) according to thefollowing formula: $C_{OUT} = \left\{ \begin{matrix}0 & \left. {if} \middle| {\xi(n)} \middle| {< \left| {\xi\left( {n - 1} \right)} \right|} \right. \\1 & \left. {if} \middle| {\xi(n)} \middle| {\geq \left| {\xi\left( {n - 1} \right)} \right|} \right.\end{matrix} \right.$

The output of the comparator controls a switch 76 selecting the newvalue S_(M)(n) or the previous output value stored in a register 78.

The device previously described allows the fine synchronization of adigital telecommunication receiver by means of a method, for maintainingfine alignment between the incoming spread spectrum signal and a locallygenerated code, comprising the following steps:

storing a plurality of consecutive samples E−1, E, M, L, L+1 of anincoming spread spectrum signal in a delay line 56;

determining by interpolation between consecutive samples of the incomingspread spectrum signal, by means of a first digitally controlledinterpolator 26, an interpolated early sample (e) anticipating anoptimal sampling time instant;

determining by interpolation between consecutive samples of the incomingspread spectrum signal, by means of a second digitally controlledinterpolator 24, an interpolated middle sample (m) corresponding to theoptimal sampling time instant;

determining by interpolation between consecutive samples of the incomingspread spectrum signal, by means of a third digitally controlledinterpolator 28, an interpolated late sample (l) delayed with respect tothe optimal sampling time instant;

calculating an error signal ξ as the difference between the energy ofthe symbols computed from the interpolated early (e) and late (l)samples;

generating, from error signal ξ a control signal S_(OUT) for controllingthe interpolation phase of the second digitally controlled interpolator24.

In particular the last step, the step of generating the control signalS_(OUT), comprises:.

extracting the sign of the error signal ξ, by means of block 66;

accumulating the sign of the error signal ξ for the generation of anintermediate control signal S_(M);

calculating the absolute value |ξ| of the error signal ξ at a timeinstant n, by means of block 70;

comparing the absolute value |ξ(n)| of the error signal ξ at timeinstant n with the absolute value |ξ(n−1)| of the error signal ξ at aprevious time instant n−1;

updating the control signal S_(OUT) to the value of the intermediatecontrol signal S_(M) if the absolute value |ξ(n)| of the error signal attime n is smaller than the absolute value |ξ(n−1)| of the same errorsignal at time n−1, maintaining otherwise unchanged the value of thecontrol signal S_(OUT).

The step of comparing the absolute value |ξ| of the error signal ξcomprises:

storing the absolute value |ξ(n−1)| of the error signal ξ in a firstregister, maintaining such absolute value |ξ(n−1)| in register 72 atleast until a new absolute value |ξ(n)| of the error signal ξ has beencalculated;

comparing the new absolute value |ξ(n)| of the error signal ξ with theabsolute value |ξ(n−1)| stored in register 72, and storing the newabsolute value |ξ(n)| in register 72, overwriting the absolute value|ξ(n−1)| previously stored.

The step of updating the control signal S_(OUT) comprises:

storing the value of the previous output signal S_(OUT)(n−1) in a secondregister 78, maintaining such value in register 78 at least until a newvalue of the intermediate control signal S_(M) has been calculated;

overwriting the value of the previous output signal S_(OUT)(n−1) storedin register 78 with the new value of the intermediate control signalS_(M) if the absolute value |ξ(n)| of the error signal at time n issmaller than the absolute value |ξ(n−1) | of the same error signal attime n−1, maintaining otherwise unchanged the value stored in register78.

1. A method for fine synchronization of a digital telecommunicationreceiver, comprising a code tracking process for maintaining finealignment between an incoming spread spectrum signal and a locallygenerated code, said method comprising: storing a plurality ofconsecutive samples (E−1, E, M, L, L+1) of said incoming spread spectrumsignal in a delay line (56); determining by interpolation betweenconsecutive samples of said incoming spread spectrum signal, by means ofa first (26) digitally controlled interpolator, an interpolated earlysample (e) anticipating an optimal sampling time instant; determining byinterpolation between consecutive samples of said incoming spreadspectrum signal, by means of a second (24) digitally controlledinterpolator, an interpolated middle sample (m) corresponding to saidoptimal sampling time instant; determining by interpolation betweenconsecutive samples of said incoming spread spectrum signal, by means ofa third (28) digitally controlled interpolator, an interpolated latesample (l) delayed with respect to said optimal sampling time instant,calculating an error signal (ξ) as the difference between the energy ofthe symbols computed from said interpolated early (e) and late (l)samples; generating, from said error signal (ξ), a control signal(S_(OUT)) for controlling the interpolation phase of said seconddigitally controlled interpolator (24); characterised in that said stepof generating a control signal (S_(OUT)) comprises: extracting the signof said error signal (ξ); accumulating said sign of said error signal(ξ) for the generation of an intermediate control signal (S_(M));calculating the absolute value (|ξ|) of said error signal (ξ) at a timeinstant n; comparing said absolute value (|ξ(n)|) of said error signal(ξ) at said time instant n with the absolute value (|ξ(n−1)|) of saiderror signal (ξ) at a previous time instant n−1; updating said controlsignal (S_(OUT)) to the value of said intermediate control signal(S_(M)) if the absolute value (|ξ(n)|) of said error signal at time n issmaller than the absolute value (|ξ(n−1)|) of the same error signal attime n−1, maintaining otherwise unchanged the value of said controlsignal (S_(OUT)).
 2. A method according to claim 1, wherein said step ofaccumulating said sign of said error signal (ξ) provides that the valueaccumulated has a positive saturation value of +4 and a negative s ionvalue of −4.
 3. A method according to claim 1, when said step ofcomparing said absolute value (|ξ|) of said error signal (ξ) comprises:storing the absolute value (|ξ(n−1) |) of said error signal (ξ) in afirst register (72), maintaining such absolute value (|ξ(n−1)|) in saidregister (72) at least until a new absolute value (|ξ(n)|) of said errorsignal (ξ) has been calculated; comparing said new absolute value(|ξ(n)|) of said error signal (ξ) with the absolute value (|ξ(n−1)stored in said first register (72), and storing said new absolute value(|ξ(n)|) in said first register (72), overwriting the absolute value(|ξ(n−1)|) previously stored.
 4. A method according to claim 1, whereinsaid step of updating said control signal (S_(OUT)) comprises: storingthe value of a previous control signal (S_(OUT)(n−1)) in a secondregister (78), maintaining such value in said second register (78) atleast until a new value of said intermediate control signal (S_(M)) hasbeen calculated; overwriting the value of said control signal(S_(OUT)(n)) stored in said second register (78) with the new value ofsaid intermediate control signal (S_(M)) if the absolute value (|ξ(n)|)of said error signal at time n is smaller than the absolute value(|ξ(n−1)|) of the same error signal at time n−1, maintaining otherwiseunchanged the value stored in said second register (78).
 5. A digitalcommunication receiver comprising a device for maintaining finealignment between an incoming spread spectrum signal and a locallygenerated code, said device comprising: a delay line (56) for storing aplurality of consecutive samples (E−1, E, M, L, L+1) of said incomingspread spectrum signal; a first digitally controlled interpolator (26)for determining by interpolation between consecutive samples stored insaid delay line (56) an interpolated early sample (e) anticipating anoptimal sampling time instant; a second digitally controlledinterpolator (24) for determining by interpolation between consecutivesamples stored in said delay line (56) an interpolated middle sample (m)corresponding to said optimal sampling time instant; a third digitallycontrolled interpolator (28) for determining by interpolation betweenconsecutive samples stored in said delay line (56) an interpolated latesample (l) delayed with respect to said optimal sampling time instant;at least a correlator (30, 32, 22) for calculating an error signal (ξ)as the difference between the energy of the symbols computed from saidinterpolated early (e) and late (l) samples; a circuit for generating acontrol signal (S_(OUT)) for controlling the interpolation phase of saidsecond digitally controlled interpolator (24); characterised in thatsaid means for generating a control signal (S_(OUT)) comprises: acircuit (23) for extracting the sign of said error signal (ξ); a circuit(66) for accumulating said sign of said error signal (ξ) in a register,for the generation of an intermediate control signal (S_(M)); a circuit(70) for calculating the absolute value (|ξ(n)|) of said error signal(ξ) at a time instant n; at least a comparator (72, 74) for comparingsaid absolute value (|ξ(n)|) of said error signal (ξ) at said timeinstant n with the absolute value (|ξ(n−1)|) of said error signal (ξ) ata previous time instant n−1; a controllable switch (76, 78) for updatingsaid control signal (S_(OUT)) to the value of said intermediate controlsignal (S_(M)) if the absolute value (|ξ(n)|) of said error signal attime n is smaller than the absolute value (|ξ(n−1)|) of the same errorsignal at time n−1, maintaining otherwise unchanged the value of saidcontrol signal (S_(OUT)).
 6. A digital communication receiver accordingto claim 5, wherein said register in which is accumulated the sign ofsaid error signal (ξ) has a positive saturation value of +4 and anegative saturation value of −4.
 7. A digital communication receiveraccording to claim 5, wherein said at least one comparator (72, 74) forcomparing said absolute value (|ξ(n)|) of said error sign (ξ) comprises:a first register (72) for storing the absolute value (|ξ(n−1)|) of saiderror signal (ξ) at a time instant n−1, maintaining such absolute value(|ξ(n−1)|) in said register (72) at least until a new absolute value(|ξ(n)|) of said error signal (ξ) has been calculated; a comparator (74)for comparing said new absolute value (|ξ(n)|) of said error signal (ξ)with the absolute value (|ξ(n−1)|) stored in said first register (72),generating a signal (C_(OUT)) indicating whether said new absolute value(|ξ(n)|) is smaller than the previously stored absolute value(|ξ(n−1)|).
 8. A digital communication receiver according to claim 7,wherein said controllable switch (76, 78) for updating said controlsignal (S_(OUT)) comprises: a second register (78) for storing the valueof a previous control signal (S_(OUT)(n−1)), maintaining such value insaid register (78) at least until a new value of said intermediatecontrol signal (S_(M)) has been calculated; a switch (76), controlled bythe signal (C_(OUT)) generated by said comparator (74), for storing insaid second register (78) a new value of said control signal(S_(OUT)(n)), if said new absolute value (|ξ(n)|) is smaller than thepreviously stored absolute value (|ξ(n−1)|), or for leaving unalteredthe value stored in the same register (78) if such condition is notverified.